Digital Design with Verilog

#verilog #rtl-design #digital-logic View on GitHub →

Digital Design with Verilog

Completed several digital design projects with Verilog, all available on GitHub. Designed and tested projects including:

Pipelined arithmetic datapath
Priority encoders
Shift registers
Flip flops

These projects cover digital logic design, RTL development, and hardware verification fundamentals developed through coursework and independent experimentation.

View all Verilog projects on GitHub