Digital Design with Verilog
Pipelined arithmetic datapath, priority encoders, shift registers, and flip flops — designed and tested in Verilog.
B.Tech Electronics & Communication Engineering student at Amrita Vishwa Vidyapeetham. Interested in digital hardware design, VLSI, RTL design, and semiconductor engineering.
I am an Electronics and Communication Engineering undergraduate interested in digital hardware design and semiconductor engineering. My primary technical interests are VLSI design, RTL development, digital verification, and computer architecture. I enjoy understanding how digital systems work at the hardware level and translating concepts into practical implementations through HDL-based design and experimentation.
I have been developing my understanding of Verilog, SystemVerilog, digital electronics, and hardware design workflows through coursework, independent projects, and hands-on experimentation. I am particularly interested in the semiconductor industry and opportunities to work on real-world hardware design and verification problems.
Pipelined arithmetic datapath, priority encoders, shift registers, and flip flops — designed and tested in Verilog.
Shrike Lite FPGA board and RP2040-based control — bitstream programming, digital logic, and GPIO interfacing.
Ongoing research project using computer vision to assist blind and visually impaired individuals during social interactions.
Welcome to my portfolio. I document my electronics endeavors, hardware experiments, and notes on digital design and VLSI.